Industry-grade semiconductor training — designed and delivered by practising ASIC engineers, for the students stepping into the global VLSI workforce.
That gap is the opening. Pragnix pairs a complete RTL-to-GDSII curriculum with an AI-EDA module no competing program offers — a genuine first-mover position, ready to take to colleges and corporates today.
Fast-start revenue from standalone workshops, and a flagship program that takes a student from MOSFET physics all the way to a tapeout-ready GDSII.
Five self-contained, campus-deliverable workshops — each ready to run in four to six weeks.
A six-month hybrid program — 22 modules and a full-tapeout capstone, evaluated by a panel of industry VLSI engineers.
Each workshop stands alone and is priced per student. Recommended delivery order below.
MOSFET to GDSII, taught live on a completed RISC-V ASIC — floorplan, placement, routing, signoff.
The single most in-demand skill gap in VLSI hiring today — setup/hold, SDC, PVT, OCV, MCMM.
Where DFT theory meets physical-design reality — scan chains, ATPG, MBIST, scan-aware placement.
Automation fluency that cuts manual effort in every EDA flow — practical from Day 1.
The differentiation workshop. DSO.ai, Cerebrus, Calibre AI, RL placement — saleable as a standalone corporate session.
Reshape scope around the specific colleges or companies in your network.
The capstone runs the complete industry flow end-to-end — the same path a real SoC takes to silicon. Pass bar: 0 DRC violations, timing closed in at least two corners.
A structured spine — foundations, automation, front-end, then the physical-design core.
No institution in India currently teaches AI-assisted physical design. Pragnix frames it through a "Two Waves" model — so students understand both the tools of today and the role of tomorrow.
DSO.ai (Synopsys), Cerebrus (Cadence), Calibre AI (Siemens), Google RL placement — steering AI-driven PD decisions in live flows.
How the engineer's job itself shifts — and how to position a career for the AI era before the market catches up.
Students train on the commercial suite the industry actually ships with — plus open-source for practice — all against a reference RISC-V ASIC clocking 152 MHz with zero DRC violations.
Every graduate leaves with proof of real capability — not attendance. The capstone is judged on the same bar the industry uses at tapeout.
Curriculum and instruction come from practising ASIC engineers — not lecturers reading from textbooks. Every concept is anchored to what happens on live silicon.
RFIC passive modelling & ASIC physical design engineer. Designs the full curriculum and leads capstone evaluation.
Live instruction by working physical-design engineers, with ongoing mentorship throughout every program.
Structured access to semiconductor engineers working on live tapeouts — a component no competing program offers.
The first workshop can be ready within two to three weeks of alignment. Tell us about your colleges or network and we'll take it from there.
We'll be in touch shortly. Talk soon.